zephyr: dts: arm: Incorrect GIC interrupt spec order for AArch64 SoCs

I noticed in the devicetree_unfixed.h that Priority and Flags are swapped in the parsed interrupts property.

We have been specifying interrupts like below:

interrupts = <type irq_num irq_priority irq_flags>;
where,
type = GIC_SPI/GIC_PPI
irq_num = interrupt number relative to type base
irq_priority = IRQ_DEFAULT_PRIORITY(0xa) / desired priority
irq_flags = IRQ_TYPE_LEVEL/IRQ_TYPE_EDGE

For example:

&uart0 {
        interrupt-parent = <&gic>;
        interrupts = <GIC_SPI 24 IRQ_DEFAULT_PRIORITY
                      IRQ_TYPE_LEVEL>;
};

For this DT parsing script has generated below @ devicetree_unfixed.h:

#define DT_N_S_soc_S_uart_40020000_IRQ_IDX_0_VAL_irq 56
#define DT_N_S_soc_S_uart_40020000_IRQ_IDX_0_VAL_flags 10
#define DT_N_S_soc_S_uart_40020000_IRQ_IDX_0_VAL_priority 0

It can be seen that flags and priority has been swapped.

So, either we can modify parsing logic or swap DT properties.