zephyr: Data corruption in STM32 SPI driver in Slave Mode

Describe the bug There is a problem with STM32 SPI driver using SLAVE mode with DMA. We can observe 2 problematic cases:

1. Driver SPI transmission can be enabled during ongoing data transmission (when CS is active), which produces garbage data (data frame is shifted).
2. Data transmission start can occur after enabling SPI bus and before enabling DMA - we can observe strange bits shifts, which may be caused because of that.

We are using STM32WB55.

To Reproduce To reproduce this behavior extra device is needed, which will be in the role of SPI master device. Bug can be seen when master device sends frame to the slave device and then is polling (with very small period) for an answer.

Expected behavior

1. Master sends command to slave, and it starts polling for an answer (if slave do not put any data to SPI (DMA buffer) then master should read zeros on SPI bus).
2. Slave device receives command from master, and it starts command processing (during that time master is sending polling frame with small period, for example 50 us).
3. After slave has prepared an answer then answer content it is put for sending over SPI (in this case into DMA buffer), and it is transmitted during next polling frame (after CS is activated).
4. Master receives unchanged answer from slave.

Logs and console output We have captured our problem on oscillograms.

Channels description:

1. SPI CS active low
2. SPI CLK
3. SPI MISO
4. This is extra signal, which was added for debug purposes. It is controlled by STM32 SPI driver (spi_ll_stm32.c) in transceive_dma function. It is set to 1 when calling LL_SPI_Enable(spi); and set to 0 when calling LL_SPI_EnableDMAReq_RX(spi); and LL_SPI_EnableDMAReq_TX(spi); Thanks to that signal we can observe what is happening between enabling SPI and DMA and also we can notice if DMA is enabled during active transmission.

Case 1: DMA is enabled during active transmission Result: Data shifted to right by 1 byte - we expected 0001000000010010 and received 0000000000010000

Figure 1: Enabling DMA during active transmission

Case 2. We can observe strange data shift by 5 bits - it can be caused by enabling SPI before DMA

Figure 2: Whole transmission appear between enabling SPI and enabling DMA

Figure 3: Enabling DMA and receiving data shifted by 5 bits - we expected 0001000000010010 and received 0000000010000000

Additional context SPI settings: CONFIG_SPI=y CONFIG_SPI_ASYNC=y CONFIG_SPI_STM32=y CONFIG_SPI_STM32_USE_HW_SS=y CONFIG_SPI_STM32_INTERRUPT=n