yosys: ERROR: Mismatch in directionality for cell port...

Steps to reproduce the issue

Possibly the same issue as https://github.com/YosysHQ/yosys/issues/2053

My code uses arrays where some lines are inputs and some are outputs. With recent Yosys builds, some small part of this code is that used to work for a long time is no-longer compiling. The code still functions in Vivado, fyi.

Boiled down, the following snippet illustrates this.

There is a 9-bit array, which is marked as inout because of the mix of signals. The subordinate module, worker assigns the parts of the bundle.

module worker(
        inout  [8:0] data_in,
        inout  [8:0] data_out
    );
    assign data_out[7:0] = data_in[7:0];
    assign data_in[ 8 ] = data_out[ 8 ];
endmodule

module tests_tbx (
        inout [8:0] data
    );
    wire [8:0] data_shadow;
    assign data_shadow[7:0] = 8'H55;
    worker w( data_shadow, data );
endmodule

Expected behavior

This should compile.

Actual behavior

$ make
yosys -q -p 'synth_ice40 -top tests_tbx -json tests_tbx.json' ../projects/tests_tbx/tests_tbx.v
ERROR: Mismatch in directionality for cell port tests_tbx.w.data_in: \data_shadow <= \w.data_in
Makefile:30: recipe for target 'tests_tbx.json' failed
make: *** [tests_tbx.json] Error 1