OpenLane: FP_IO_MIN_DISTANCE does not affect the capacity of pin in placement

Description

I am trying to create a MACRO using OpenLane.

This macro is a part of the wrapper design, and will be reused many time in the wrapper module. The input and output signals is huge (about 9000+), so that I get the error information in STEP 4

[INFO]: Running IO Placement (log: designs/CellSARA/runs/30Percent_IO/logs/floorplan/4-place_io.log)...
[ERROR]: during executing: "openroad -exit -no_init -python /openlane/scripts/odbpy/io_place.py --config /openlane/designs/CellSARA/pin_order.cfg --hor-layer met3 --ver-layer met2 --ver-width-mult 2 --hor-width-mult 2 --hor-extension 0
--ver-extension 0 --length 4 --unmatched-error --input-lef /openlane/designs/CellSARA/runs/30Percent_IO/tmp/merged.nom.lef --output-def /openlane/designs/CellSARA/runs/30Percent_IO/tmp/floorplan/4-io.def --output /openlane/designs/CellS
ARA/runs/30Percent_IO/tmp/floorplan/4-io.odb /openlane/designs/CellSARA/runs/30Percent_IO/tmp/floorplan/3-initial_fp.odb |& tee /dev/null /openlane/designs/CellSARA/runs/30Percent_IO/logs/floorplan/4-place_io.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
OpenROAD 1a1617d908d2ebdb731de9ab4e3d9fd93a6dcf97
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Top-level design name: CellSARA
Block boundaries: 0 0 954980 965700
Horizontal Tracks Origin: 340, Count: 1420, Step: 680
Vertical Tracks Origin: 230, Count: 2076, Step: 460
There are more pins/virtual_pins: 2542, than places to put them: 2076. Try making your floorplan area larger.
child process exited abnormally

It appears that the floorplan area is insufficient to accommodate all pins, and I have observed some gaps between pins in the SPM design. Therefore, I suppose that adjusting the distance between pins might enable the floorplan to accommodate more pins.

I found that there is a parameter FP_IO_MIN_DISTANCE, which the default value is 3. so I set it to 0.2 in config.json.

the config.json are:

{
    "DESIGN_NAME": "CellSARA",
    "VERILOG_FILES": "dir::src/*.v",
    "CLOCK_PORT": "clk",
    "CLOCK_PERIOD": 10.0,
    "DESIGN_IS_CORE": false,
    "FP_PDN_CORE_RING": false,
    "FP_IO_MIN_DISTANCE": 0.20,
    "FP_CORE_UTIL": 30,
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg"
}

However, even after re-running the flow, I still encounter the same error message. It appears that changing FP_IO_MIN_DISTANCE does not impact the pin placement capacity.

Expected Behavior

By reducing the FP_IO_MIN_DISTANCE value, the pin placement capacity will increase.

Environment report

Kernel: Linux v5.4.0-87-generic
Distribution: ubuntu 18.04
Python: v3.8.3 (OK)
Container Engine: docker v20.10.7 (OK)
OpenLane Git Version: e5a7a0976918035d1a4312ac9965148f215aa4ed
pip: INSTALLED
python-venv: INSTALLED
---
PDK Version Verification Status: OK
---
Git Log (Last 3 Commits)

e5a7a09 2023-03-22T15:29:01+02:00 Rework Placement (#1684) - Mohamed Gaber -  (grafted, HEAD -> master, tag: 2023.03.23, origin/master, origin/HEAD)
---
Git Remotes

origin  https://github.com/The-OpenROAD-Project/OpenLane.git (fetch)
origin  https://github.com/The-OpenROAD-Project/OpenLane.git (push)

Reproduction material

CellSARA.zip

Relevant log output

OpenLane Container (e5a7a09):/openlane$ ./flow.tcl -design CellSARA -tag 30Percent_IO -overwrite
OpenLane e5a7a0976918035d1a4312ac9965148f215aa4ed
All rights reserved. (c) 2020-2022 Efabless Corporation and contributors.
Available under the Apache License, version 2.0. See the LICENSE file for more details.

[INFO]: Using configuration in 'designs/CellSARA/config.json'...
[INFO]: PDK Root: /home/hanm/.volare
[INFO]: Process Design Kit: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd
[INFO]: Run Directory: /openlane/designs/CellSARA/runs/30Percent_IO
[INFO]: Removing existing /openlane/designs/CellSARA/runs/30Percent_IO...
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[STEP 1]                                                                                                                                                                                                                           [249/376]
[INFO]: Running Synthesis (log: designs/CellSARA/runs/30Percent_IO/logs/synthesis/1-synthesis.log)...
[STEP 2]
[INFO]: Running Single-Corner Static Timing Analysis (log: designs/CellSARA/runs/30Percent_IO/logs/synthesis/2-sta.log)...
[STEP 3]
[INFO]: Running Initial Floorplanning (log: designs/CellSARA/runs/30Percent_IO/logs/floorplan/3-initial_fp.log)...
[INFO]: Floorplanned with width 943.92 and height 943.84.
[STEP 4]
[INFO]: Running IO Placement (log: designs/CellSARA/runs/30Percent_IO/logs/floorplan/4-place_io.log)...
[ERROR]: during executing: "openroad -exit -no_init -python /openlane/scripts/odbpy/io_place.py --config /openlane/designs/CellSARA/pin_order.cfg --hor-layer met3 --ver-layer met2 --ver-width-mult 2 --hor-width-mult 2 --hor-extension 0
--ver-extension 0 --length 4 --unmatched-error --input-lef /openlane/designs/CellSARA/runs/30Percent_IO/tmp/merged.nom.lef --output-def /openlane/designs/CellSARA/runs/30Percent_IO/tmp/floorplan/4-io.def --output /openlane/designs/CellS
ARA/runs/30Percent_IO/tmp/floorplan/4-io.odb /openlane/designs/CellSARA/runs/30Percent_IO/tmp/floorplan/3-initial_fp.odb |& tee /dev/null /openlane/designs/CellSARA/runs/30Percent_IO/logs/floorplan/4-place_io.log"
[ERROR]: Exit code: 1
[ERROR]: Last 10 lines:
OpenROAD 1a1617d908d2ebdb731de9ab4e3d9fd93a6dcf97
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Top-level design name: CellSARA
Block boundaries: 0 0 954980 965700
Horizontal Tracks Origin: 340, Count: 1420, Step: 680
Vertical Tracks Origin: 230, Count: 2076, Step: 460
There are more pins/virtual_pins: 2542, than places to put them: 2076. Try making your floorplan area larger.
child process exited abnormally

[INFO]: Saving current set of views in 'designs/CellSARA/runs/30Percent_IO/results/final'...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at 'designs/CellSARA/runs/30Percent_IO/reports/manufacturability.rpt'.
[INFO]: Created metrics report at 'designs/CellSARA/runs/30Percent_IO/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.