OpenLane: Failed at Routing congestion too high.

Description

I got Routing congestion too high. error at [INFO]: Running Global Routing Resizer Timing Optimizations....

I have try different CELL_PAD, because flow may failed at Running Placement Resizer Design Optimizations for [ERROR DPL-0036] Detailed placement failed.

I have try to reduce the area cost by deleting my cache, which will use sky130_sram_1kbyte_1rw1r_32x256_8. And the area have reduced from about 75% to 30%, and I believe the design is small enough.

The design is generated from chisel3 by the way.

Expected behavior

Environment

WSL2 Ubuntu22.04 memory:64GB memory CPU:5950x

https://github.com/efabless/caravel_user_project

Reproduction Material

https://github.com/whutddk/Rift2Go_2330 commit:f20a84a79b6f4c09912288111236692d2a24fbe6

Logs

###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]
[INFO]: Setting signal min routing layer to: met1 and clock min routing layer to met1. 
[INFO]: Setting signal max routing layer to: met4 and clock max routing layer to met4. 
-congestion_iterations 500 -verbose
[INFO GRT-0020] Min routing layer: met1
[INFO GRT-0021] Max routing layer: met4
[INFO GRT-0022] Global adjustment: 30%
[INFO GRT-0023] Grid origin: (0, 0)
[INFO GRT-0043] No OR_DEFAULT vias defined.
[INFO GRT-0088] Layer li1     Track-Pitch = 0.4600  line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met1    Track-Pitch = 0.3400  line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met2    Track-Pitch = 0.4600  line-2-Via Pitch: 0.3500
[INFO GRT-0088] Layer met3    Track-Pitch = 0.6800  line-2-Via Pitch: 0.6150
[INFO GRT-0088] Layer met4    Track-Pitch = 0.9200  line-2-Via Pitch: 0.6150
[INFO GRT-0019] Found 7322 clock nets.
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 21
[INFO GRT-0003] Macros: 0
[INFO GRT-0004] Blockages: 555977

[INFO GRT-0053] Routing resources analysis:
          Routing      Original      Derated      Resource
Layer     Direction    Resources     Resources    Reduction (%)
---------------------------------------------------------------
li1        Vertical            0             0          0.00%
met1       Horizontal    4314600       2240323          48.08%
met2       Vertical      3235950       2153568          33.45%
met3       Horizontal    2157300       1507384          30.13%
met4       Vertical      1510110        863264          42.83%
---------------------------------------------------------------

[INFO GRT-0101] Running extra iterations to remove overflow.
[WARNING GRT-0227] Reached 20 congestion iterations with less than 15% of reduction between iterations.
[INFO GRT-0197] Via related to pin nodes: 2031525
[INFO GRT-0198] Via related Steiner nodes: 103541
[INFO GRT-0199] Via filling finished.
[INFO GRT-0111] Final number of vias: 3213759
[INFO GRT-0112] Final usage 3D: 16188314
[ERROR GRT-0118] Routing congestion too high.
Error: resizer_routing_timing.tcl, 53 GRT-0118

About this issue

  • Original URL
  • State: closed
  • Created 2 years ago
  • Comments: 16 (1 by maintainers)

Most upvoted comments

Check your pdks its already available.

% more pdks/sky130B/libs.ref/sky130_sram_macros/verilog/s
sky130_sram_1kbyte_1rw1r_32x256_8.v  sky130_sram_1kbyte_1rw1r_8x1024_8.v  sky130_sram_2kbyte_1rw1r_32x512_8.v  sram_1rw1r_32_256_8_sky130.v

If required size not exist, you can generate from here