stlink: [STM32G031]: can't connect to target: unknown chip id (--connect-under-reset not working)

Programmer/board type: stlink v3 mini
Operating system and version: Windows
Stlink tools version : 1.6.1
Stlink commandline tool name: st-flash
Target chip (and board if applicable): STM32G031

Commandline-Output:

st-flash --connect-under-reset --debug erase
st-flash 1.6.1
2021-03-10T13:43:30 DEBUG common.c: *** looking up stlink version
2021-03-10T13:43:30 DEBUG common.c: st vid         = 0x0483 (expect 0x0483)
2021-03-10T13:43:30 DEBUG common.c: stlink pid     = 0x374e
2021-03-10T13:43:30 DEBUG common.c: stlink version = 0x3
2021-03-10T13:43:30 DEBUG common.c: jtag version   = 0x7
2021-03-10T13:43:30 DEBUG common.c: swim version   = 0x0
2021-03-10T13:43:30 DEBUG common.c:     notice: the firmware doesn't support a swim interface
2021-03-10T13:43:30 DEBUG common.c: *** looking up stlink version
2021-03-10T13:43:30 DEBUG common.c: st vid         = 0x0483 (expect 0x0483)
2021-03-10T13:43:30 DEBUG common.c: stlink pid     = 0x374e
2021-03-10T13:43:30 DEBUG common.c: stlink version = 0x3
2021-03-10T13:43:30 DEBUG common.c: jtag version   = 0x7
2021-03-10T13:43:30 DEBUG common.c: swim version   = 0x0
2021-03-10T13:43:30 DEBUG common.c:     notice: the firmware doesn't support a swim interface
2021-03-10T13:43:30 DEBUG common.c: stlink current mode: mass
2021-03-10T13:43:30 DEBUG usb.c: JTAG/SWD freq set to 0
2021-03-10T13:43:30 DEBUG common.c: *** set_swdclk ***
2021-03-10T13:43:30 INFO usb.c: Unable to match requested speed 1800 kHz, using 1000 kHz
2021-03-10T13:43:30 DEBUG common.c: stlink current mode: mass
2021-03-10T13:43:30 DEBUG common.c: *** stlink_enter_swd_mode ***
2021-03-10T13:43:30 DEBUG common.c: *** stlink_jtag_reset ***
2021-03-10T13:43:30 DEBUG common.c: *** stlink_reset ***
2021-03-10T13:43:30 DEBUG common.c: *** stlink_write_debug32 5fa0004 to 0xe000ed0c
2021-03-10T13:43:30 DEBUG common.c: Loading device parameters....
2021-03-10T13:43:30 DEBUG common.c: *** stlink_core_id ***
2021-03-10T13:43:30 DEBUG common.c: core_id = 0x000003e8
2021-03-10T13:43:30 DEBUG common.c: *** stlink_read_debug32 3e8 is 0xe0042000
2021-03-10T13:43:30 WARN common.c: unknown chip id! 0x3e8
Failed to connect to target

Expected/description: my board uses swd and swclk gpios, so in order to connect with mcu stlink must connect under reset conditions, while it works perfectly fine using STM32CubeProgrammer (connect under reset option is selected), st-flash fails to read chip id It looks like --connect-under-reset param doesn’t have any effect. At the same time, I can use the same st-flash config to program all my other boards.

STM32CubeProgrammer log:

13:57:38 : ST-LINK SN : 001A003E3137511433333639
13:57:38 : ST-LINK FW : V3J7M2
13:57:38 : Voltage : 3.33V
13:57:38 : SWD freq : 24000 KHz
13:57:38 : Connect mode: Under Reset
13:57:38 : Reset mode : Software reset
13:57:38 : Device ID : 0x466
13:57:38 : UPLOADING OPTION BYTES DATA ...
13:57:38 : Bank : 0x00
13:57:38 : Address : 0x40022020
13:57:38 : Size : 32 Bytes
13:57:38 : Bank : 0x01
13:57:38 : Address : 0x40022080
13:57:38 : Size : 16 Bytes
13:57:38 : UPLOADING ...
13:57:38 : Size : 1024 Bytes
13:57:38 : Address : 0x8000000
13:57:38 : Read progress:
13:57:38 : Data read successfully
13:57:38 : Time elapsed during the read operation is: 00:00:00.001

About this issue

Original URL
State: closed
Created 3 years ago
Comments: 55 (7 by maintainers)

Commits related to this issue

Fix incorrect STM32H7_CORE_ID value The STM32H7_CORE_ID value in the manual is 0x6b00477, however it was incorrectly set in stm32.h to 0x6b002477 Fixes #1098 — committed to C-Elegans/stlink by C-Elegans 3 years ago

Most upvoted comments

@kwarek I tried to make the connect under reset more stable. This option seems to work better:

int stlink_target_connect(stlink_t *sl, enum connect_type connect) {
  uint32_t dhcsr;

  if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) {
    stlink_enter_swd_mode(sl);
  }

  if (connect == CONNECT_UNDER_RESET) {
    /* Try to halted core before reset. It need for stop core without 
     * connect NRST pin before any init procedure */
    unsigned timeout = time_ms() + 5;
    while (time_ms() < timeout) {
      sl->backend->force_debug(sl);
      usleep(100);
    }

    /* Reset core throught NRST pin
     * Minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset)*/
    stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW);
    usleep(20);
    // clear S_RESET_ST in DHCSR register
    stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr);
    stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH);

    /* Try to halted core after reset */
    timeout = time_ms() + 10;
    while (time_ms() < timeout) {
      sl->backend->force_debug(sl);
      usleep(100);
    }

    /* Check reset flag */
    dhcsr = 0;
    stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr);
    if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) {
      printf("NRST is not connected\n");
    }

    /* addition soft reset for halt before the first instruction */
    stlink_soft_reset(sl, 1 /* halt on reset */);
  } else if (connect == CONNECT_NORMAL) {
    stlink_reset(sl, RESET_AUTO);
  }

  return stlink_load_device_params(sl);
}

Ant-ON on Apr 27, 2021