siliconcompiler: RePlace divergence detected error

[NesterovSolve] Iter: 700 overflow: 0.583543 HPWL: 956226
[NesterovSolve] Iter: 710 overflow: 0.579076 HPWL: 958131
[NesterovSolve] Iter: 720 overflow: 0.569644 HPWL: 965507
[NesterovSolve] Iter: 730 overflow: 0.5577 HPWL: 974746
[NesterovSolve] Iter: 740 overflow: 0.548687 HPWL: 981041
[NesterovSolve] Iter: 750 overflow: 0.542512 HPWL: 986448
[NesterovSolve] Iter: 760 overflow: 0.5396 HPWL: 1001737
[NesterovSolve] Iter: 770 overflow: 0.538572 HPWL: 1016441
[NesterovSolve] Iter: 780 overflow: 0.537715 HPWL: 1027078
[NesterovSolve] Iter: 790 overflow: 0.537715 HPWL: 1033658
[NesterovSolve] Iter: 800 overflow: 0.537715 HPWL: 1040998
[NesterovSolve] Iter: 810 overflow: 0.537715 HPWL: 1051940
[NesterovSolve] Iter: 820 overflow: 0.537715 HPWL: 1061126
[NesterovSolve] Iter: 830 overflow: 0.537715 HPWL: 1069578
[NesterovSolve] Iter: 840 overflow: 0.537715 HPWL: 1073897
[NesterovSolve] Iter: 850 overflow: 0.537715 HPWL: 1077300
[NesterovSolve] Iter: 860 overflow: 0.537715 HPWL: 1081346
[NesterovSolve] Iter: 870 overflow: 0.537715 HPWL: 1076083
[NesterovSolve] Iter: 880 overflow: 0.537715 HPWL: 1072078
[NesterovSolve] Iter: 890 overflow: 0.537715 HPWL: 1065461
[NesterovSolve] Iter: 900 overflow: 0.532552 HPWL: 1050625
[NesterovSolve] Iter: 910 overflow: 0.502432 HPWL: 1042669
[NesterovSolve] Iter: 920 overflow: 0.44268 HPWL: 1025777
[NesterovSolve] Iter: 930 overflow: 0.442549 HPWL: 1029223
[NesterovSolve] Iter: 940 overflow: 0.473972 HPWL: 1004714
[NesterovSolve] Iter: 950 overflow: 0.458905 HPWL: 997280
[NesterovSolve] Iter: 960 overflow: 0.443377 HPWL: 1009753
[NesterovSolve] Iter: 970 overflow: 0.380633 HPWL: 1019671
[NesterovSolve] Iter: 980 overflow: 0.367137 HPWL: 1018329
[ERROR GPL-0307] RePlAce divergence detected. Re-run with a smaller max_phi_cof value.
Error: sc_place.tcl, 17 GPL-0307
| WARNING | job0  | place      | 0  | Command failed with code 1. See log file /home/ryancor/Desktop/Digital-Designs/XOR_String/build/xor_string_encryption/job0/place/0/place.log
| ERROR   | job0  | place      | 0  | Halting step 'place' index '0' due to errors.
| ERROR   | job0  | cts        | 0  | Halting step due to previous error in place0
| ERROR   | job0  | cts        | 0  | Halting step 'cts' index '0' due to errors.
| ERROR   | job0  | route      | 0  | Halting step due to previous error in cts0
| ERROR   | job0  | route      | 0  | Halting step 'route' index '0' due to errors.
| ERROR   | job0  | dfm        | 0  | Halting step due to previous error in route0
| ERROR   | job0  | dfm        | 0  | Halting step 'dfm' index '0' due to errors.
| ERROR   | job0  | export     | 0  | Halting step due to previous error in dfm0
| ERROR   | job0  | export     | 0  | Halting step 'export' index '0' due to errors.
| ERROR   | job0  | export     | 1  | Halting step due to previous error in dfm0
| ERROR   | job0  | export     | 1  | Halting step 'export' index '1' due to errors.
Traceback (most recent call last):
  File "build.py", line 13, in <module>
    main()
  File "build.py", line 8, in main
    chip.run()
  File "/home/ryancor/Desktop/siliconcompiler/siliconcompiler/core.py", line 4463, in run
    self.error('Run() failed, see previous errors.', fatal=True)
  File "/home/ryancor/Desktop/siliconcompiler/siliconcompiler/core.py", line 5025, in error
    raise SiliconCompilerError(msg) from None
siliconcompiler.core.SiliconCompilerError: Run() failed, see previous errors.

i’ve gotten this error before with smaller verilog files but now it seems to be pretty persistent, dont know why I’m getting this error. Here is my verilog file in test along with my build.py

import siliconcompiler

def main():
    chip = siliconcompiler.Chip('xor_string_encryption')
    chip.set('input', 'rtl', 'verilog', 'xor_string_encryption.v')
    chip.clock('clk', period=10)
    chip.load_target('freepdk45_demo')
    chip.run()
    chip.summary()
    chip.show()

if __name__ == '__main__':
    main()

module xor_string_encryption(
  input clk,
  input rst,
  input [7:0] data_in,
  output reg [7:0] data_out
);

  reg [7:0] key;

  always @(posedge clk) begin
    if(rst) begin
      key <= 8'h0;
    end
    else begin
      key <= 8'b10101010;
    end
  end

  always @(posedge clk) begin
    if(rst) begin
      data_out <= 8'h0;
    end
    else begin
      data_out <= data_in ^ key;
    end
  end

endmodule