probe-rs: Can't connect to STM32WL55JC MCU
Probe-rs does not seem to work with STM32WL55JC MCUs. Segger tools and openocd work fine.
Using a nucleo-WL55JC1 dev-kit on Arch Linux.
with on-board st-link
> RUST_LOG=debug probe-rs-cli reset --chip STM32WL55JCIx --speed 200
DEBUG probe_rs::config::registry > Searching registry for chip with name STM32WL55JCIx
DEBUG probe_rs::config::registry > Exact match for chip name: STM32WL55JCIx
DEBUG probe_rs::probe::cmsisdap::tools > Searching for CMSIS-DAP probes using libusb
DEBUG probe_rs::probe::cmsisdap::tools > Found 0 CMSIS-DAP probes using libusb, searching HID
DEBUG probe_rs::probe::cmsisdap::tools > Found 0 CMSIS-DAP probes total
DEBUG jaylink > libusb 1.0.26.11724
DEBUG jaylink > libusb has capability API: true
DEBUG jaylink > libusb has HID access: true
DEBUG jaylink > libusb has hotplug support: true
DEBUG jaylink > libusb can detach kernel driver: true
DEBUG probe_rs::probe::cmsisdap::tools > Attempting to open 0483:374e in CMSIS-DAP v1 mode
DEBUG probe_rs::probe::stlink::usb_interface > Acquired libusb context.
DEBUG probe_rs::probe::stlink::usb_interface > Aquired handle for probe
DEBUG probe_rs::probe::stlink::usb_interface > Active config descriptor: ConfigDescriptor { bLength: 9, bDescriptorType: 2, wTotalLength: 128, bNumInterfaces: 4, bConfigurationValue: 1, iConfiguration: 4, bmAttributes: 128, bMaxPower: 250, extra: [] }
DEBUG probe_rs::probe::stlink::usb_interface > Device descriptor: DeviceDescriptor { bLength: 18, bDescriptorType: 1, bcdUSB: 512, bDeviceClass: 239, bDeviceSubClass: 2, bDeviceProtocol: 1, bMaxPacketSize: 64, idVendor: 1155, idProduct: 14158, bcdDevice: 256, iManufacturer: 1, iProduct: 2, iSerialNumber: 3, bNumConfigurations: 1 }
DEBUG probe_rs::probe::stlink::usb_interface > Claimed interface 0 of USB device.
DEBUG probe_rs::probe::stlink::usb_interface > Succesfully attached to STLink.
DEBUG probe_rs::probe::stlink > Initializing STLink...
DEBUG probe_rs::probe::stlink > Current device mode: MassStorage
DEBUG probe_rs::probe::stlink > STLink version: (3, 9)
DEBUG probe_rs::probe::stlink > attach(Swd)
DEBUG probe_rs::probe::stlink > Current device mode: MassStorage
DEBUG probe_rs::probe::stlink > Switching protocol to SWD
INFO probe_rs::probe::stlink > Target voltage (VAPP): 3.28 V
DEBUG probe_rs::probe::stlink > Successfully initialized SWD.
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::probe::stlink > Opening AP 0
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x24770011
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::probe::stlink > Opening AP 1
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x84770001
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::probe::stlink > Opening AP 2
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x0
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x24770011
DEBUG probe_rs::architecture::arm::ap > Reading register BASE
DEBUG probe_rs::architecture::arm::ap > Read register BASE, value=0xe00ff003
DEBUG probe_rs::architecture::arm::ap > Reading register BASE2
DEBUG probe_rs::architecture::arm::ap > Read register BASE2, value=0x0
DEBUG probe_rs::architecture::arm::ap > Reading register CSW
DEBUG probe_rs::architecture::arm::ap > Read register CSW, value=0x23000052
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 1, HNONSEC: 1, PROT: 6, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U8 }
DEBUG probe_rs::architecture::arm::ap > Reading register CSW
DEBUG probe_rs::architecture::arm::ap > Read register CSW, value=0x23000050
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 0, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 1, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::communication_interface > HNONSEC supported: false
DEBUG probe_rs::architecture::arm::ap > Reading register CFG
DEBUG probe_rs::architecture::arm::ap > Read register CFG, value=0x0
DEBUG probe_rs::probe::stlink > AP ApAddress {
dp: Default,
ap: 0x0,
}: MemoryAp(MemoryApInformation { address: ApAddress { dp: Default, ap: 0 }, only_32bit_data_size: false, debug_base_address: 3759140864, supports_hnonsec: false, has_large_address_extension: false, has_large_data_extension: false })
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x84770001
DEBUG probe_rs::architecture::arm::ap > Reading register BASE
DEBUG probe_rs::architecture::arm::ap > Read register BASE, value=0xf0000003
DEBUG probe_rs::architecture::arm::ap > Reading register BASE2
DEBUG probe_rs::architecture::arm::ap > Read register BASE2, value=0x0
DEBUG probe_rs::architecture::arm::ap > Reading register CSW
DEBUG probe_rs::architecture::arm::ap > Read register CSW, value=0x43800042
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 1, HNONSEC: 1, PROT: 6, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U8 }
DEBUG probe_rs::architecture::arm::ap > Reading register CSW
DEBUG probe_rs::architecture::arm::ap > Read register CSW, value=0x43800050
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 0, CACHE: 3, SPIDEN: 1, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 1, AddrInc: Off, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::communication_interface > HNONSEC supported: true
DEBUG probe_rs::architecture::arm::ap > Reading register CFG
DEBUG probe_rs::architecture::arm::ap > Read register CFG, value=0x0
DEBUG probe_rs::probe::stlink > AP ApAddress {
dp: Default,
ap: 0x1,
}: MemoryAp(MemoryApInformation { address: ApAddress { dp: Default, ap: 1 }, only_32bit_data_size: false, debug_base_address: 4026531840, supports_hnonsec: true, has_large_address_extension: false, has_large_data_extension: false })
DEBUG probe_rs::probe::stlink > Read mem 32 bit, address=e000edf0, length=4
DEBUG probe_rs::probe::stlink > Read mem 32 bit, address=e000edf0, length=4
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > send_jtag_command 242 got SwdDpWait, retrying
WARN probe_rs::probe::stlink > too many retries, giving up
DEBUG probe_rs::probe::stlink > Current device mode: Jtag
Error: Connecting to the chip was unsuccessful.
Caused by:
0: An error with the usage of the probe occurred
1: An error specific to a probe type occurred
2: Command failed with status SwdDpWait
with external jlink
> RUST_LOG=debug probe-rs-cli reset --chip STM32WL55JCIx --speed 200
DEBUG probe_rs::config::registry > Searching registry for chip with name STM32WL55JCIx
DEBUG probe_rs::config::registry > Exact match for chip name: STM32WL55JCIx
DEBUG probe_rs::probe::cmsisdap::tools > Searching for CMSIS-DAP probes using libusb
DEBUG probe_rs::probe::cmsisdap::tools > Found 0 CMSIS-DAP probes using libusb, searching HID
DEBUG probe_rs::probe::cmsisdap::tools > Found 0 CMSIS-DAP probes total
DEBUG jaylink > libusb 1.0.26.11724
DEBUG jaylink > libusb has capability API: true
DEBUG jaylink > libusb has HID access: true
DEBUG jaylink > libusb has hotplug support: true
DEBUG jaylink > libusb can detach kernel driver: true
DEBUG jaylink > open_usb: device descriptor: DeviceDescriptor {
bLength: 0x12,
bDescriptorType: 0x1,
bcdUSB: 0x200,
bDeviceClass: 0x0,
bDeviceSubClass: 0x0,
bDeviceProtocol: 0x0,
bMaxPacketSize: 0x40,
idVendor: 0x1366,
idProduct: 0x101,
bcdDevice: 0x100,
iManufacturer: 0x1,
iProduct: 0x2,
iSerialNumber: 0x3,
bNumConfigurations: 0x1,
}
DEBUG jaylink > scanning 1 interfaces
DEBUG jaylink > J-Link interface is #0
DEBUG jaylink > legacy caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx
DEBUG jaylink::capabilities > unknown ext. capability bits: 0x18B54FB17C1DB9FF7BBF truncated to 0x1B9FF7BBF (Reserved0 | GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)
DEBUG jaylink > extended caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
DEBUG probe_rs::probe::cmsisdap::tools > Attempting to open 1366:0101 in CMSIS-DAP v1 mode
DEBUG probe_rs::probe::stlink::usb_interface > Acquired libusb context.
DEBUG jaylink > open_usb: device descriptor: DeviceDescriptor {
bLength: 0x12,
bDescriptorType: 0x1,
bcdUSB: 0x200,
bDeviceClass: 0x0,
bDeviceSubClass: 0x0,
bDeviceProtocol: 0x0,
bMaxPacketSize: 0x40,
idVendor: 0x1366,
idProduct: 0x101,
bcdDevice: 0x100,
iManufacturer: 0x1,
iProduct: 0x2,
iSerialNumber: 0x3,
bNumConfigurations: 0x1,
}
DEBUG jaylink > scanning 1 interfaces
DEBUG jaylink > J-Link interface is #0
DEBUG jaylink > legacy caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx
DEBUG jaylink::capabilities > unknown ext. capability bits: 0x18B54FB17C1DB9FF7BBF truncated to 0x1B9FF7BBF (Reserved0 | GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite)
DEBUG jaylink > extended caps: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
DEBUG probe_rs::probe::jlink > J-Link returned interface Fine, which is not supported by probe-rs.
DEBUG probe_rs::probe::jlink > J-Link returned interface Pic32Icsp, which is not supported by probe-rs.
DEBUG probe_rs::probe::jlink > J-Link returned interface Spi, which is not supported by probe-rs.
DEBUG probe_rs::probe::jlink > J-Link returned interface C2, which is not supported by probe-rs.
DEBUG probe_rs::probe::jlink > J-Link returned interface CJtag, which is not supported by probe-rs.
DEBUG probe_rs::probe::jlink > J-Link returned interface Mc2WireJtag, which is not supported by probe-rs.
DEBUG probe_rs::probe::jlink > Supported speeds: SpeedInfo { base_freq: 180000000, min_div: 12 }
DEBUG probe_rs::probe::jlink > Attaching to J-Link
DEBUG probe_rs::probe::jlink > Attaching with protocol 'SWD'
INFO probe_rs::probe::jlink > J-Link: S/N: 260108677
DEBUG probe_rs::probe::jlink > J-Link: Capabilities: GetHwVersion | WriteDcc | AdaptiveClocking | ReadConfig | WriteConfig | WriteMem | ReadMem | SpeedInfo | GetMaxBlockSize | GetHwInfo | SetKsPower | ResetStopTimed | MeasureRtckReact | SelectIf | RwMemArm79 | GetCounters | ReadDcc | GetCpuCaps | ExecCpuCmd | Swo | WriteDccEx | Register | Indicators | TestNetSpeed | GetCapsEx | HwJtagWrite
INFO probe_rs::probe::jlink > J-Link: Firmware version: J-Link V10 compiled Sep 22 2022 14:59:36
INFO probe_rs::probe::jlink > J-Link: Hardware version: J-Link 10.10.0
INFO probe_rs::probe::jlink > J-Link: Target voltage: 3.35 V
DEBUG probe_rs::probe::jlink > Attached succesfully
DEBUG probe_rs::probe::jlink::arm > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(6ba02477)
DEBUG probe_rs::architecture::arm::communication_interface > Selecting DP Default
DEBUG probe_rs::architecture::arm::dp > Writing DP register ABORT, value=0x0000001e
DEBUG probe_rs::probe::jlink::arm > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x00000000
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::dp > Reading DP register CTRL/STAT
DEBUG probe_rs::probe::jlink::arm > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(8000040)
DEBUG probe_rs::architecture::arm::dp > Read DP register CTRL/STAT, value=0x08000040
DEBUG probe_rs::architecture::arm::dp > Writing DP register CTRL/STAT, value=0x50000000
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::dp > Reading DP register CTRL/STAT
DEBUG probe_rs::probe::jlink::arm > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(f8000040)
DEBUG probe_rs::architecture::arm::dp > Read DP register CTRL/STAT, value=0xf8000040
DEBUG probe_rs::architecture::arm::dp > Writing DP register CTRL/STAT, value=0x50000f00
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::dp > Reading DP register CTRL/STAT
DEBUG probe_rs::probe::jlink::arm > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(f8000f40)
DEBUG probe_rs::architecture::arm::dp > Read DP register CTRL/STAT, value=0xf8000f40
DEBUG probe_rs::architecture::arm::dp > Reading DP register CTRL/STAT
DEBUG probe_rs::probe::jlink::arm > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(f8000f40)
DEBUG probe_rs::architecture::arm::dp > Read DP register CTRL/STAT, value=0xf8000f40
DEBUG probe_rs::architecture::arm::dp > Writing DP register CTRL/STAT, value=0xf8000f41
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x000000f0
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(24770011)
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x24770011
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 1, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x010000f0
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(24770011)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(24770011)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(84770001)
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x84770001
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 2, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x020000f0
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(84770001)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(84770001)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x0
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x000000f0
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(24770011)
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x24770011
DEBUG probe_rs::architecture::arm::ap > Reading register BASE
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(24770011)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(e00ff003)
DEBUG probe_rs::architecture::arm::ap > Read register BASE, value=0xe00ff003
DEBUG probe_rs::architecture::arm::ap > Reading register BASE2
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(e00ff003)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::ap > Read register BASE2, value=0x0
DEBUG probe_rs::architecture::arm::ap > Reading register CSW
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 0
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x00000000
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(23000040)
DEBUG probe_rs::architecture::arm::ap > Read register CSW, value=0x23000040
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 1, HNONSEC: 1, PROT: 6, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U8 }
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(23000040)
DEBUG probe_rs::architecture::arm::ap > Reading register CSW
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(23000040)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(23000050)
DEBUG probe_rs::architecture::arm::ap > Read register CSW, value=0x23000050
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 0, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 1, AddrInc: Off, _RES1: 0, SIZE: U8 }
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(23000050)
DEBUG probe_rs::architecture::arm::communication_interface > HNONSEC supported: false
DEBUG probe_rs::architecture::arm::ap > Reading register CFG
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x000000f0
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(23000050)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(23000050)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::ap > Read register CFG, value=0x0
DEBUG probe_rs::architecture::arm::communication_interface > AP GenericAp { address: ApAddress { dp: Default, ap: 0 } }: MemoryAp(MemoryApInformation { address: ApAddress { dp: Default, ap: 0 }, only_32bit_data_size: false, debug_base_address: 3759140864, supports_hnonsec: false, has_large_address_extension: false, has_large_data_extension: false })
DEBUG probe_rs::architecture::arm::ap > Reading register IDR
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 1, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x010000f0
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(84770001)
DEBUG probe_rs::architecture::arm::ap > Read register IDR, value=0x84770001
DEBUG probe_rs::architecture::arm::ap > Reading register BASE
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(84770001)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(f0000003)
DEBUG probe_rs::architecture::arm::ap > Read register BASE, value=0xf0000003
DEBUG probe_rs::architecture::arm::ap > Reading register BASE2
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(f0000003)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::ap > Read register BASE2, value=0x0
DEBUG probe_rs::architecture::arm::ap > Reading register CSW
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 1, AP_BANK_SEL to 0
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x01000000
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(43800042)
DEBUG probe_rs::architecture::arm::ap > Read register CSW, value=0x43800042
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 1, HNONSEC: 1, PROT: 6, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U8 }
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(43800042)
DEBUG probe_rs::architecture::arm::ap > Reading register CSW
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(43800042)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(43800050)
DEBUG probe_rs::architecture::arm::ap > Read register CSW, value=0x43800050
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 0, CACHE: 3, SPIDEN: 1, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 1, AddrInc: Off, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(43800050)
DEBUG probe_rs::architecture::arm::communication_interface > HNONSEC supported: true
DEBUG probe_rs::architecture::arm::ap > Reading register CFG
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 1, AP_BANK_SEL to 15
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x010000f0
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(43800050)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(43800050)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::ap > Read register CFG, value=0x0
DEBUG probe_rs::architecture::arm::communication_interface > AP GenericAp { address: ApAddress { dp: Default, ap: 1 } }: MemoryAp(MemoryApInformation { address: ApAddress { dp: Default, ap: 1 }, only_32bit_data_size: false, debug_base_address: 4026531840, supports_hnonsec: true, has_large_address_extension: false, has_large_data_extension: false })
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 1, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 0, AP_BANK_SEL to 0
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x00000000
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(0)
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(3050000)
DEBUG probe_rs::architecture::arm::ap > Read register DRW, value=0x3050000
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(3050000)
DEBUG probe_rs::architecture::arm::ap > Writing register DRW, value=DRW { data: a05f0001 }
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(3050000)
DEBUG probe_rs::architecture::arm::ap > Writing register CSW, value=CSW { DbgSwEnable: 0, HNONSEC: 0, PROT: 2, CACHE: 3, SPIDEN: 0, _RES0: 0, MTE: 0, Type: 0, Mode: 0, TrinProg: 0, DeviceEn: 0, AddrInc: Single, _RES1: 0, SIZE: U32 }
DEBUG probe_rs::architecture::arm::communication_interface > Changing AP to 1, AP_BANK_SEL to 0
DEBUG probe_rs::architecture::arm::dp > Writing DP register SELECT, value=0x01000000
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(3050000)
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(3050000)
DEBUG probe_rs::architecture::arm::ap > Writing register TAR, value=TAR { address: e000edf0 }
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Ok(3050000)
DEBUG probe_rs::architecture::arm::ap > Reading register DRW
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(3050000)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Err(WaitResponse)
DEBUG probe_rs::probe::jlink::arm > DAP WAIT, (read), retries remaining 1000.
DEBUG probe_rs::probe::jlink::arm > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
DEBUG probe_rs::probe::jlink::arm > Cleared sticky overrun bit
DEBUG probe_rs::probe::jlink::arm > Performing 2 transfers (1 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Err(WaitResponse)
DEBUG probe_rs::probe::jlink::arm > Transfer result 1: Err(FaultResponse)
DEBUG probe_rs::probe::jlink::arm > DAP FAULT
DEBUG probe_rs::probe::jlink::arm > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(f8000f03)
DEBUG probe_rs::probe::jlink::arm > Reading DAP register failed. Ctrl/Stat register value is: Ctrl {
.0: 4160753411,
csyspwrupack: true,
csyspwrupreq: true,
cdbgpwrupack: true,
cdbgpwrupreq: true,
cdbgrstack: true,
c_dbg_rst_req: false,
trn_cnt: 0,
mask_lane: 15,
w_data_err: false,
read_ok: false,
sticky_err: false,
stick_cmp: false,
trn_mode: 0,
sticky_orun: true,
orun_detect: true,
}
DEBUG probe_rs::probe::jlink::arm > Performing 1 transfers (0 additional transfers)
DEBUG probe_rs::probe::jlink::arm > Transfer result 0: Ok(0)
Error: Connecting to the chip was unsuccessful.
Caused by:
0: A core architecture specific error occurred
1: Failed to read register DRW at address 0x0000000c
2: An error specific to the selected architecture occurred
3: Target device responded with a FAULT response to the request.
About this issue
- Original URL
- State: open
- Created 2 years ago
- Comments: 26 (18 by maintainers)
I’m using probe-run in CI with the embedded STLink on the nucleo boards for the stm32wlxx-hal, still works on v0.3.9. I can try your specific command this weekend if I remember.
@newAM I believe he is running into this with onboard STLink v3. I appreciate you confirming that you can still connect … it helps eliminate some stuff.