skywater-pdk: At least one cell (sky130_fd_sc_hd__clkdlybuf4s15_1) violates SkyWater's own DRC rules and needs to be fixed.

The cell in question (sky130_fd_sc_hd__clkdlyabuf4s15_1) contains a poly overlap error (poly overlaps contact by 0.07um, where an overlap of 0.08um is required). There is no indication in the documentation that this rule can be waived, and there is no reason that the overlap can’t just be extended to meet the rule. I does not compromise the standard cell circuit in any way.

The GDS of the cell needs to be fixed. Note that the above cell has two such errors in it.

I will fix the GDS and post the corrected version. If any other such examples come up, add them to this issue.

About this issue

Original URL
State: open
Created 4 years ago
Comments: 19 (2 by maintainers)

Most upvoted comments

@ax3ghazy / @antonblanchard - We should set this up as an automated check to run on pull requests to this repository.

mithro on Mar 7, 2021

@ax3ghazy I did run with drc(full). Here’s the magic TCL script (does it cover everything?):

gds read $::env(GDS_FILE)
select top cell
drc euclidean on
drc style drc(full)
drc check
set drcresult [drc listall why]

set outfile [open "drc-errors.txt" a ]
puts $outfile $::env(GDS_FILE)

foreach {errtype coordlist} $drcresult {
	puts $outfile $errtype
}

close $outfile

exit

Run with:

for i in $(find . -name '*.gds'); do
        GDS_FILE=$i magic -noconsole -dnull -T pdk/sky130A/libs.tech/magic/sky130A.tech drc-test.tcl
done

@RTimothyEdwards do you want me to run the same test across the other libraries?

antonblanchard on Mar 5, 2021

The first two of these layouts were corrected in pull request #2 to https://github.com/efabless/skywater-pdk-libs-sky130_fd_sc_hd fork, which automatically updates the upstream repos. Leave this issue open until all layouts have been corrected.

RTimothyEdwards on Mar 5, 2021

I had a quick check of all the sky130_fd_sc_hd cells, and I could only find one additional cell that had a poly overlap issue. The full list:

sky130_fd_sc_hd__clkdlybuf4s15_1
sky130_fd_sc_hd__clkdlybuf4s18_1
sky130_fd_sc_hd__buf_16
sky130_fd_sc_hd__a2111oi_0

I did notice a few other DRC issues:

sky130_fd_sc_hd__probe_p_8:
Metal5 overlap of via4.< 0.12um (met5.3 - via4.4)

sky130_fd_sc_hd__tapvgnd_1:
Metal1 minimum area < 0.083um^2 (met1.6)

sky130_fd_sc_hd__tapvgnd2_1:
Metal1 minimum area < 0.083um^2 (met1.6)

antonblanchard on Feb 7, 2021