runtime: [x86] SequenceEqual returns false for equal spans

Yep!!. I got a repro on my mail machine that is Intel (CoffeLake), but runs Win11.

the last tracked piece - porting to 3.1 has been completed. Closing.

Should this be reopened to track the need for servicing backport?

AMD cpuid does not report ERMSB (is there a way to check?)

CPU-Z is not very detailed but the CoreInfo -f (from SysInternals) should be detailed enough. For reference, this is the output on AMD Ryzen 7 5700G where ERMSB is listed as supported:

Coreinfo v3.52 - Dump information on system CPU and memory topology
Copyright (C) 2008-2021 Mark Russinovich
Sysinternals - www.sysinternals.com


AMD Ryzen 7 5700G with Radeon Graphics
AMD64 Family 25 Model 80 Stepping 0, AuthenticAMD
Microcode signature: 00000000
HTT             *       Multicore
CET             *       Supports Control Flow Enforcement Technology
Kernel CET      -       Kernel-mode CET Enabled
User CET        *       User-mode CET Allowed
HYPERVISOR      *       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             -       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          -       Supports AMD SKINIT
SGX             -       Supports Intel SGX

NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            *       Supports Supervisor Mode Access Prevention
PAGE1GB         *       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              -       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          *       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           *       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             *       Supports AES extensions
AVX             *       Supports AVX instruction extensions
AVX2            *       Supports AVX2 instruction extensions
AVX-512-F       -       Supports AVX-512 Foundation instructions
AVX-512-DQ      -       Supports AVX-512 double and quadword instructions
AVX-512-IFAMA   -       Supports AVX-512 integer Fused multiply-add instructions
AVX-512-PF      -       Supports AVX-512 prefetch instructions
AVX-512-ER      -       Supports AVX-512 exponential and reciprocal instructions
AVX-512-CD      -       Supports AVX-512 conflict detection instructions
AVX-512-BW      -       Supports AVX-512 byte and word instructions
AVX-512-VL      -       Supports AVX-512 vector length instructions
FMA             *       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          *       Supports RDRAND instruction
RDSEED          *       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            *       Supports bit manipulation extensions 1
BMI2            *       Supports bit manipulation extensions 2
ADX             *       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            *       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           *       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         *       Supports MONITOR and MWAIT instructions
MOVBE           *       Supports MOVBE instruction
ERMSB           *       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           *       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          -       Can write history of 64-bit branch addresses
DS              -       Implements memory-resident debug buffer
DS-CPL          -       Supports Debug Store feature with CPL
PCID            -       Supports PCIDs and settable CR4.PCIDE
INVPCID         *       Supports INVPCID instruction
PDCM            -       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
TSC-INVARIANT   *       TSC runs at constant rate
xTPR            -       Supports disabling task priority messages

EIST            -       Supports Enhanced Intel Speedstep
ACPI            -       Implements MSR for power management
TM              -       Implements thermal monitor circuitry
TM2             -       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          -       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             -       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       *       Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 0000000D (Basic), 80000021 (Extended).
Maximum implemented address width: 48 bits (virtual), 48 bits (physical).

Processor signature: 00A50F00

Once we have a full fix, we will likely be taking the fix down level to all supported versions.

Actually, it reproduces even on 6.0.100 SDK, so the range may be much bigger than I anticipated, or there is some external trigger factor.

Update: Also 5.0.403 SDK when I converted the code to Marshal.Alloc/FreeHGlobal.

Where should I ship the machine to? 😂 More realistically, happy to give access to it or test anything that comes along.

I will take a look. I have AMD machines.

@jkotas appologies for that, I’ve applied the following change

- $env:COMPlus_LogFacility=0x00080001
+ $env:COMPlus_LogFacility="0x00080001"

re-run the tests and uploaded all the files here

I’ve pushed my exact repro to https://github.com/adamsitnik/runtime/tree/issue65292repro

And uploaded full dump to OneDrive

I am on:

Author:			Jakob Botsch Nielsen <Jakob.botsch.nielsen@gmail.com>
Date:			1 day ago (2/14/2022 11:08:08 AM)
Committer:		GitHub <noreply@github.com>
Commit hash:	e23382c32bf03d3fea5a2f1157a99148a51ca3f4
Child:			Commit index
Parent:			6e05d78d

Keep information about CSE defs on assignment nodes (#64896)

Reuse the gtCSEnum field on assignments to signal "this is a performed
CSE def". gtCanSwapOrder uses the CSE def information to reason about
evaluation order, so without keeping this information we could risk
substitution a CSE def, followed by reordering operands, and then
finally substituting a CSE use.

Fix #64883
Contained in branches:
main

Thanks for the minimal repro, looking at it now

Total number of differences: 0 out of 10485760

It seems to be a bug in System.Memory or codegen, as SequenceEquals returns true, but the helper fails to find any differences:

https://github.com/dotnet/runtime/blob/e23382c32bf03d3fea5a2f1157a99148a51ca3f4/src/libraries/Common/tests/TestUtilities/System/AssertExtensions.cs#L445-L471

I was able to reproduce it using the following test:

public class Repro
{
    [Fact]
    public void TryToMimic()
    {
        while (true)
        {
            byte[] writerBytes = RandomNumberGenerator.GetBytes(10 * 1024 * 1024);
            var readerBytes = new byte[writerBytes.Length];

            writerBytes.CopyTo(readerBytes, 0);

            Assert.True(writerBytes.SequenceEqual(readerBytes));
        }
    }
}

@EgorBo is there any chance you could take a look?