amaranth: platform.add_clock_constraint does not work for instances with lattice diamond for machxo2

Similiar to #373 platform.add_clock_constraint does not work for instances in lattice diamond. However, the same fix does not seem to be applicable. Do you have any ideas what is going wrong?

repro:

from amaranth import *
from amaranth.build import *
from amaranth_boards.tinyfpga_ax2 import *

class Test(Elaboratable):
    def elaborate(self, plat):
        m = Module()
        clk = Signal()
        m.submodules.inst = Instance("JTAGF", o_JTCK=clk)

        m.domains += ClockDomain("sync")
        m.d.comb += ClockSignal().eq(clk)

        plat.add_clock_constraint(clk, 2e6)

        plat.add_resources([Resource("gpio", 0, Pins("1", conn=("gpio", 0), dir="o"), Attrs(IOSTANDARD="LVCMOS33"))])
        gpio0 = plat.request("gpio", 0)
        m.d.sync += gpio0.o.eq(~gpio0)

        return m

TinyFPGAAX2Platform().build(Test())

About this issue

  • Original URL
  • State: open
  • Created 4 years ago
  • Comments: 16 (16 by maintainers)

Most upvoted comments

Or maybe use set_hierarchy_separator {/} ?